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PRELIMINARY
CY7C1327G
4-Mbit (256K x 18) Pipelined Sync SRAM
Features
* Registered inputs and outputs for pipelined operation * 256K x18 common I/O architecture * 3.3V core power supply * 3.3V / 2.5V I/O operation * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) -- 2.6 ns (for 225-MHz device) -- 2.8 ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) -- 4.0 ns (for 133-MHz device) -- 4.5 ns (for 100-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * Lead-Free 100-pin TQFP and 119 Ball BGA packages. * "ZZ" Sleep Mode Option
Functional Description[1]
The CY7C1327G SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1327G operates from a +3.3V core power supply while all outputs also operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5compatible.
Logic Block Diagram
A0, A1, A
MODE
ADDRESS REGISTER
2 A[1:0]
ADV CLK
BURST Q1 COUNTER AND LOGIC CLR Q0
ADSC
ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER MEMORY ARRAY BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER DQA,DQPA WRITE REGISTER DQA,DQPA WRITE DRIVER SENSE AMPS
BWB
OUTPUT REGISTERS
OUTPUT BUFFERS
E
DQs DQPA DQPB
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
1
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com
Cypress Semiconductor Corporation Document #: 38-05519 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised October 21, 2004
PRELIMINARY
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 325 40 225 MHz 2.6 290 40 200 MHz 2.8 265 40 166 MHz 3.5 240 40 133 MHz 4.0 225 40
CY7C1327G
100 MHz 4.5 205 40 Unit ns mA mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
BYTE B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP CY7C1327G
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
BYTE A
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MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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PRELIMINARY
Pin Configurations
119-ball BGA 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ 2 A CE2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A NC 3 A A A VSS VSS VSS BWB VSS NC VSS Vss VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC NC 5 A A A VSS VSS VSS Vss VSS NC VSS BWA VSS VSS VSS NC A NC 6 A CE3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ
CY7C1327G
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PRELIMINARY
Pin Definitions
Name A0, A1, A I/O Description
CY7C1327G
BWA,BWB GW BWE CLK CE1 CE2
InputAddress Inputs used to select one of the 256K address locations. Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter. InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be Synchronous asserted LOW to conduct a byte write. InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
CE3
OE
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputZZ "sleep" Input, active HIGH. This input, when High places the device in a non-time-critical Asynchronous "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by "A" during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition. Power Supply Power supply inputs to the core of the device. Ground I/O Ground InputStatic Ground for the device. Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not internally connected to the die.
ADV ADSP
ZZ
ADSC DQA, DQB DQPA, DQPB VDD VSS VDDQ MODE
NC
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PRELIMINARY
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1327G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW[A:B]) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW is HIGH,
CY7C1327G
then the Write operation is controlled by BWE and BW[A:B] signals. The CY7C1327G provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:B]) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1327G is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:B]) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to DQ is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1327G is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1327G provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
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PRELIMINARY
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
CY7C1327G
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
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PRELIMINARY
Truth Table[ 2, 3, 4, 5, 6]
Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Add. Used None None None None None External External CE1 H L L L L L L X X H H X X H H X H L X H X H X CE2 X X L X L H H X X X X X X X X X X H X X X X X CE3 X H X H X L L X X X X X X X X X X L X X X X X ZZ L L L L L L L L L L L L L L L L L L L L L L H ADSP X L L H H L H H H X X H H X X H X H H X H X X ADSC L X X L L X L H H H H H H H H H H H H H H H X ADV X X X X X X X L L L L H H H H H H X H H H H X OE X X X X X X X H L H L H L H L X X X X X X X X
CY7C1327G
DQ tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state DQ tri-state DQ tri-state DQ tri-state DQ tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state
WRITE X X X X X X H H H H H H H H H L L L L L L L X
Continue Read Next Continue Read Next Continue Read Next Continue Read Next Suspend Read Current Suspend Read Current Suspend Read Current Suspend Read Current Begin Write Begin Write Begin Write Current Current External
Continue Write Next Continue Write Next Suspend Write Current Suspend Write Current ZZ "Sleep" None
Truth Table for Read/Write[2]
Function Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write All Bytes Write All Bytes GW H H H H H H L BWE H L L L L L X BWB X H H L L L X BWA X H L H L L X
Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in tri-state ............................................ -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V
CY7C1327G
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Ambient Range Temperature VDD VDDQ Commercial 0C to +70C 3.3V -5%/+10% 2.5V -5% to VDD Industrial -40C to +85C
Electrical Characteristics Over the Operating Range [7, 8]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[7] Voltage[7] VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -1.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Input Load Current except ZZ and MODE GND VI VDDQ 2.0 1.7 -0.3 -0.3 -5 -30 5 -5 30 -5 5 325 290 265 240 225 205 120 115 110 100 90 80 40 4-ns cycle,250MHz 4.4-ns cycle,225MHz 5-ns cycle,200MHz 6-ns cycle,166MHz 7.5-ns cycle,133MHz 10-ns cycle,100MHz ISB1 Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC 4-ns cycle,250MHz 4.4-ns cycle,225MHz 5-ns cycle,200MHz 6-ns cycle,166MHz 7.5-ns cycle,133MHz 10-ns cycle,100MHz ISB2 Automatic CE VDD = Max, Device Power-down Deselected, VIN 0.3V or Current--CMOS Inputs VIN > VDDQ - 0.3V, f = 0 All speeds Test Conditions Min. 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD Unit V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
Shaded areas contain advance information. Notes: 7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 8. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
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PRELIMINARY
Electrical Characteristics Over the Operating Range (continued)[7, 8]
Parameter ISB3 Description Test Conditions 4-ns cycle,250MHz 4.4-ns cycle,225MHz 5-ns cycle,200MHz 6-ns cycle,166MHz 7.5-ns cycle,133MHz 10-ns cycle,100MHz ISB4 Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 All speeds Min.
CY7C1327G
Max. 105 100 95 85 75 65 45 Unit mA mA mA mA mA mA mA
Automatic CE VDD = Max, Device Power-down Deselected, or VIN 0.3V Current--CMOS Inputs or VIN > VDDQ - 0.3V f = fMAX = 1/tCYC
Thermal Resistance[9]
Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package TBD TBD BGA Package TBD TBD Unit C/W C/W
JA JC
Capacitance[9]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V TQFP Package 5 5 5 BGA Package Unit 5 5 7 pF pF pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF R = 351 R = 317 ALL INPUT PULSES VDDQ 10% GND 1ns 90% 90% 10% 1ns
VT = 1.5V
(a) 2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V
INCLUDING JIG AND SCOPE
(b)
R = 1667 VDDQ 10%
(c)
ALL INPUT PULSES 90% 90% 10% 1ns
OUTPUT RL = 50 5 pF R =1538 VT = 1.25V INCLUDING JIG AND SCOPE
GND 1ns
(a)
(b)
(c)
Notes: 9. Tested initially and after any design or process change that may affect these parameters.
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PRELIMINARY
Switching Characteristics Over the Operating Range[14, 15]
250 MHz Parameter tPOWER Description VDD(Typical) to the first[10] 1 4.0 1.7 1.7 2.6 1.0 0 2.6 2.6 0 2.6 0 2.6 1.0 0 2.6 2.6 0 2.8 225 MHz 1 4.4 2.0 2.0 2.6 1.0 0 2.8 2.8 0 3.5 200 MHz 1 5.0 2.0 2.0 2.8 1.5 0 3.5 3.5 0 166 MHz 1 6.0 2.5 2.5 3.5 1.5 0
CY7C1327G
133 MHz 1 7.5 3.0 3.0 4.0 1.5 0 4.0 4.5 0 4.0 4.5 4.5 4.5 100 MHz 1 10 3.5 3.5 4.5 ms ns ns ns ns ns ns ns ns ns ns
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max Unit
Clock tCYC Clock Cycle Time Clock HIGH tCH Clock LOW tCL Output Times Data Output Valid After CLK tCO Rise tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Data Output Hold After CLK Rise Clock to Low-Z[11, 12, 13] Clock to High-Z[11, 12, 13] OE LOW to Output Valid OE LOW to Output Low-Z[11, OE HIGH to Output High-Z
[11,
12, 13] 12, 13]
Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP , ADSC Hold After CLK Rise ADV Hold After CLK Rise GW,BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns
1.2 ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise 1.2 GW, BWE, BWX Set-up Before 1.2 CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-Up Before CLK Rise 1.2 1.2
Shaded areas contain advance information. Notes: 10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 13. This parameter is sampled and not 100% tested. 14. Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets. 15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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PRELIMINARY
Switching Waveforms
Read Cycle Timing[16]
t CYC
CY7C1327G
CLK
t CH t ADS t ADH
t CL
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
tWES tWEH
A2
A3 Burst continued with new base address
GW, BWE, BW[A:B]
tCES tCEH
Deselect cycle
CE
tADVS tADVH
ADV ADV suspends burst.
tOEV t OEHZ t CLZ t OELZ tCO tDOH t CHZ
OE
Data Out (Q)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Single READ DON'T CARE UNDEFINED
BURST READ
Burst wraps around to its initial state
Notes: 16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle Timing[16, 17]
t CYC
CY7C1327G
CLK tCH tADS ADSP ADSC extends burst tADS tADH tADH tCL
tADS ADSC tAS A1 tAH
tADH
ADDRESS
A2 Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BW[A :B] tWES tWEH GW tCES CE t t ADVS ADVH ADV ADV suspends burst tCEH
OE tDS tDH
Data In (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Document #: 38-05519 Rev. *A
Page 12 of 18
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[16, 18, 19]
tCYC
CY7C1327G
CLK
tCH tADS tADH tCL
ADSP
ADSC
tAS tAH
ADDRESS BWE, BW[A:B]
A1
A2
A3 tWES tWEH
A4
A5
A6
tCES
tCEH
CE
ADV
OE
tCO tDS tDH tOELZ High-Z tCLZ tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Data In (D)
Data Out (Q)
High-Z
Q(A1) Back-to-Back READs
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Notes: 18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 19. GW is HIGH.
Document #: 38-05519 Rev. *A
Page 13 of 18
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing [20, 21]
CLK
t ZZ t ZZREC
CY7C1327G
ZZ
t
ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Ordering Information
Speed (MHz) 250 Ordering Code CY7C1327G-250AXC CY7C1327G-250BGC CY7C1327G-250BGXC CY7C1327G-250AXI CY7C1327G-250BGI CY7C1327G-250BGXI 225 CY7C1327G-225AXC CY7C1327G-225BGC CY7C1327G-225BGXC CY7C1327G-225AXI CY7C1327G-225BGI CY7C1327G-225BGXI 200 CY7C1327G-200AXC CY7C1327G-200BGC CY7C1327G-200BGXC CY7C1327G-200AXI CY7C1327G-200BGI CY7C1327G-200BGXI Package Name A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 Package Type Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05519 Rev. *A
Page 14 of 18
PRELIMINARY
Ordering Information (continued)
Speed (MHz) 166 Ordering Code CY7C1327G-166AXC CY7C1327G-166BGC CY7C1327G-166BGXC CY7C1327G-166AXI CY7C1327G-166BGI CY7C1327G-166BGXI 133 CY7C1327G-133AXC CY7C1327G-133BGC CY7C1327G-133BGXC CY7C1327G-133AXI CY7C1327G-133BGI CY7C1327G-133BGXI 100 CY7C1327G-100AXC CY7C1327G-100BGC CY7C1327G-100BGXC CY7C1327G-100AXI CY7C1327G-100BGI CY7C1327G-100BGXI Package Name A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 Package Type
CY7C1327G
Operating Range Commercial
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball BGA (14 x 22 x 2.4mm) Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
Industrial
Commercial
Industrial
Commercial
Industrial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BG package will be available in 2005
Document #: 38-05519 Rev. *A
Page 15 of 18
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
CY7C1327G
51-85050-*A
Document #: 38-05519 Rev. *A
Page 16 of 18
PRELIMINARY
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4 mm) BG119
CY7C1327G
51-85115-*B
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05519 Rev. *A
Page 17 of 18
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY7C1327G 4-Mbit (256K x 18) Pipelined Sync SRAM Document Number: 38-05519 REV. ** *A ECN NO. 224367 278513 Issue Date See ECN See ECN Orig. of Change RKF VBL New Data Sheet Description of Change
CY7C1327G
In Ordering Info section, Changed TQFP to PB-Free TQFP Added PB-Free BG package.
Document #: 38-05519 Rev. *A
Page 18 of 18

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